The leading SOC and ASIC design services company

Everything you want to know about the technologies we employ and our innovative ways. A reflection of our expertise and excellence.

Clock Path ECO with Prime Time DMSA fix_eco_timing

Find out how Synapse Engineers have been using Prime Time- a golden sign off tool for ASIC signoff tool over the last two years. Prime Time is one of the best tools out there. It works seamlessly in different design flows no matter what implementation tool is used and it does a great job utilizing computer power to help designers speed up the timing signoff. This paper discusses our experiences as we overcame leftover violations after PT_ECO and found new ways to work with Prime Time for the clock path ECO.

UVM Harness Whitepaper

An exciting look at how a UVM Harness can be used to stitch all signals to interface in large scale projects, reducing error margins and effort. Find out how we use a collection of wires with at least two connectors at each end, to connect your module to the UVM environment. Our tests have proved that UVM Harnesses can help boost productivity and eliminate test bench connectivity problems in large scale projects.

UVM Heartbeat

Save time during simulations with UVM Heartbeat, a flexible, powerful watchdog timer that analyzes test bench activity. Learn to assemble, use and run UVM Heartbeat. Go beyond the user manuals and guides to understand UVM Heartbeat better, save time and resources.

Integrating UVM and VMM

Move away from the trend of reusing legacy verification environments with UVM adoption. Discover a newer way of integrating and merging two very different design verification environments and take a look at what happens when a VMM test bench is merged with UVM. This white paper studies the techniques used, the troubleshooting efforts and the common issues that arise from this process and discusses how to fix them.

System Modeling Services

Transaction Level Models can provide a fast and more abstract representation of hardware. Virtual Platforms for early evaluation of systems can be developed using transaction level models. Synapse Design provides modeling services to develop virtual platforms to enable early development of software and hardware.

Synapse Design Position Paper - Verification: Build or Simulate?

This paper discusses the role of FPGAs in the verification of today’s complex SoC designs.  It presents the pros/cons of using FPGAs in the overall design process, alongside the reasons UVM-based methodologies are becoming so prevalent today.

Synapse Design Position Paper - Abstractions and System Design Concepts

This paper discusses the many levels of abstraction at which a design is captured during the design process.  It presents the current status of the formats, languages and methodologies in place at each of these levels, and then discusses issues/concerns in traversing from one level to another.

Debug of SystemVerilog Assertions

SystemVerilog Assertions (SVA) are a very critical and important part of the verification flow and the creation of the testbench. There are multiple steps in creating meaningful and successful assertions, as defined in this paper.

Steering Through Verification Challenges of USB 3.0-Based SoC Using Cadence VIP

As the technology innovation marches forward, new kinds of devices, medium (internet of things), media formats and large inexpensive storage are converging. They required significantly higher bandwidth than the tradition technologies and protocols. USB3 addresses these needs by achieving higher data transfer speeds that are up to 10 times faster than the previous version of the standard, enabling rapid and efficient transfers of data to and from external storage and multimedia devices. USB3.0 utilizes a dual-bus architecture that provides backward compatibility with USB2.0.

Synapse Design Position Paper - MultiCore Designs

Hem Hingarh, VP Engineering, discusses three basic classes of multicore architectures: homogeneous multicore (with same ISA) with shared memory (PCs & Servers); heterogeneous multicore (different ISA) with mix of shared and non-shared memory; and homogeneous multicore (same ISA) with non-shared memory.

Synapse Design Position Paper - Low Power SOC Design Integration Issues

Multi-power domain SOCs are complex and present new integration challenges because many blocks have different operating modes at different voltages, different clock period and duty cycles of each block being awake, asleep or in shutdown mode. We must pay more attention to applications that dictate modes of operations, power and battery life requirements.

Synapse Design Position Paper - SOC Manufacturing & Test Trends

Hem Hingarh, VP Engineering, discusses a variety of manufacturing and test trends influencing the successful design and ramp to production for complex mixed signal and low power SOCs.