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Senior DFT Engineer, Santa Clara CA

Post date :06/13/2019
Skill Set:
 8+ years industry experience required

Skill Set: BS or above in electrical engineering or computer engineering

Experience with Hierarchical DFT Architecture

Experience using Synopsys or Mentor test tools.
Experience in Scan Insertion, test Muxing, ATPG, MBist & pre/post-layout simulation
Expertise in Top Level DFT switching with DFT Architecture experience will add value

Expertise in test clock strategy & muxing required  
Expertise in test timing constraints for shift, capture, mbist or any special mode & timing closure for these modes

Experience :

8+ years
Job Description :

Emulation Engineer, Santa Clara CA

Post date :06/13/2019
Skill Set:
 8+ year of industry experience required
  • Prior experience with hardware emulation platforms and associated tools
  • Strong background in system integration and troubleshooting
  • Strong scripting skills (Makefile, Shell, Python etc)
  • Excellent communication skills
  • Ability to work in a fast paced, exciting environment
  • Ability to work in a cross-functional setting (hardware, software, system)

 

Experience :

8+ years
Job Description :

Senior Verification Engineer, Santa Clara CA

Post date :06/13/2019
Skill Set:

1. 5+ years industry experience with BS, MS in computer science or related field

2. Experience with SystemVerilog and either OVM or UVM

3. Experience with C/C++

4. Some level of processor based verification

Experience :

8+ years
Job Description :
 
  1. Design verification of Complex processor system using Systemverilog-UVM
  2.  Create testplans and sign-off functional verification
  3.  Create testcases in C and UVM
  4.  Script/Automatize recurring mundane activities

Senior Physical Design Engineer, Santa Clara CA

Post date :06/13/2019
Skill Set:
 8+ years industry experience required

Skill Set: BS or above in electrical engineering or computer engineering

Experience with Hierarchical design or Top Level is a plus

Experience with ICC2 or Innovus
Experience in 7nm, 10nm or 16nm in required
Expertise in floorplanning large blocks with lot of memories/IPs or top level floorplan with budgeting

Expertise in power grid design

Expertise in clocks understanding & building CTS 
Expertise in low power flow (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc) is a plus
Hands on experience with Timing Closure,  DRC/LVS, LEC

Experience in IR drop analysis is a plus

Programming experience in Tcl, Perl is a plus

Involvement in flow development is a plus  

Experience :
8+ years
Job Description :